The present invention relates to a semiconductor integrated circuit (LSI) and a method of manufacture thereof; and, more particularly, the invention relates to a semiconductor integrated circuit in which there is an enhancement of the wiring density, as required by the next generation of development, in which a semiconductor integrated circuit has a miniaturized structure. For example, the present invention relates to a technique which is applicable in the formation of copper wiring by a damascene method in a semiconductor manufacturing process.
Recently, copper has been used as a wiring material for forming a semiconductor integrated circuit, since copper exhibits a low electrical resistivity, which is about ½ of the electrical resistivity of an aluminum alloy. The use of copper makes it possible to realize speed-up and miniaturization of a semiconductor integrated circuit. The copper wiring is typically formed by a damascene method, by which it is possible to overcome the problem that dry etching of copper is difficult, for example. The damascene method is a technique in which grooves are formed in an insulation film; a conductive film, such as a copper film, which constitutes a wiring material, is embedded in the grooves by plating, sputtering or the like; and, thereafter, the extra copper film outside the grooves is removed by chemical mechanical polishing (CMP), for example, so as to form conductive films in the grooves. A method which embeds a conductive film in wiring grooves and connection holes and forms wiring and plugs simultaneously is referred to as a dual damascene method, while a method which embeds a conductive film in wiring (or connection holes) and forms the wiring (or the plugs) is referred to as a single damascene method.
When the density of the wiring grooves or connection holes formed in the insulation film differs depending on the regions of a substrate where they are located, the quantity of the metal film to be removed by CMP differs between the dense regions and the coarse regions. For example, in the dense regions, a larger quantity of metal film is embedded in the wiring grooves or the wiring holes than is similarly embedded in the coarse regions; and, hence, the quantity of metal to be removed by CMP is increased in the dense regions, while the quantity of metal to be removed by CMP is decreased in the coarse regions. As a result, there arises a phenomenon in which the insulation film which remains between regions of the substrate differ in film thickness. This phenomenon is referred to as “erosion”. Further, the metal film and the insulation film (for example, a silicon oxide film) largely differ in the polishing speed thereof when using the CMP method; and, hence, there arises a phenomenon in which the metal portions (portions such as wiring grooves or connection holes) are excessively polished. This phenomenon is referred to as “dishing”. Japanese Unexamined Patent Publication 2000-3912 describes that it is necessary to hold the wiring occupying rate to equal to or less than a specific value to prevent such erosion or dishing.
For example, there is a design rule which indicates that a minimum line width is 0.2 μm and the minimum line interval is 0.2 μm; so that, when lines having the minimum width are arranged at the minimum line interval without gaps, the wiring occupying rate becomes 50%. However, in an actual LSI, there is no possibility that the lines will be arranged in such a perfect manner; and, hence, in actual manufacturing practice, the wiring occupying rate is not more than 30%, for example, in many cases.
However, to consider a case in which a width of the line is set to 0.4 μm, which is twice as large as the minimum line width, when lines having such a line width are arranged at the minimum line interval of 0.2 μm, the line occupying rate is increased to 67%. This line occupying rate is remarkably high compared to the average wiring occupying rate of 30%, and, hence, such an increase of the line width is not desirable from the viewpoint of prevention of erosion and dishing.
Here, in a case in which the line interval corresponding to these wide lines is set to 0.4 μm, the wiring occupying rate becomes 50% and approaches the average wiring occupying rate, and, hence, it is possible to obtain a preferable effect from the viewpoint of prevention of erosion and dishing.
Further, with respect to the wiring LSI of nowadays, an auto routing technique using DA (Design Automation) is usually used. Here, since the positions where lines can be arranged (wiring channels) are arranged by using a sum (basic pitch) of the minimum line width and the minimum line interval that is allowable as a reference based on a design rule, it is desirable to determine the line width and the line interval of the wide lines such that they conform to values which are an integer times as large as the basic pitch.
According to the latest miniaturized design rule, the difference between the locally high wiring occupying rate and the average wiring occupying rate, that is, an allowable wiring occupying rate, is becoming narrow. This tendency is particularly remarkable in the case of copper wiring using a damascene method. As a result, in the latest miniaturized design rule, the line width value which can be arranged with the minimum line width is becoming narrower compared to the conventional line width value.